JinLei 3200
JinLei 3200

High-Performance Chiplet Die-to-Die Interconnect IP

Chiplet-based method has become a trending technology in the field of high-performance chip design. JinLei 3200 high-performance chiplet interconnection IP is designed with a special fusion architecture, which can support a variety of interface protocols, multiple package types, and a variety of mainstream process nodes. With excellent performance and efficiency, support for safe and reliable transmission, especially ultra-low latency, it is a specialized interconnect IP solution tailored for chiplet integration.


Cloud Computing

Artificial Intelligence


Autonomous Driving

  Key Features:

Supper-High-Bandwidth, Ultra-Low-Latency, Extremely Reliable 

With excellent bandwidth density, energy efficiency and ultra-low interconnection delay, the key indicators of this IP are at the leading level in the industry. The specially 

optimized design ensures stable and reliable data communication in various scenarios. It is suitable for Chiplet Die-to-Die interconnect of high-performance computing chips, 

especially in delay-sensitive scenarios.



Fusion Architecture, Flexible Configuration

Innovative fusion architecture enables the IP to support multiple interface protocols and adapt to a variety of conventional and advanced packaging designs based on silicon

interconnect or substrate interconnect. This IP is available at multiple mainstream

process nodes, providing more and better choices to meet customers' diversified 

product needs.