Responsibilities:

1. Responsible for SOC-level or IP-level front-end design.

2. Cooperate with the verification engineer to complete the functional verification of the chip.

3. Cooperate with back-end engineers to complete the physical implementation of the chip.

Requirements:

1. Proficient in RTL design; familiar with the architecture design of complex SOC systems and AMBA bus.

2. Familiar with various processes of chip front-end: Synthesis, STA, Formal, Lint.

3. Familiar with ARM IP integration or ARM Core designers is preferred.

4. Familiar with DDR/Serdes/PCIE and other related IP designers are preferred.