Responsibilities:

1. Responsible for FPGA prototype verification of ASIC SOC.

2. Cooperate with embedded software and asic front-end designers for board-level debugging and system joint debugging.

3. Assist in the formulation of the test plan and cooperate with the completion of the final test.

4. Responsible for the preparation of technical documents.

Requirements:

1. More than 3 years of FPGA development experience, familiar with FPGA design, development process. With independent FPGA coding, simulation, debugging capabilities.

2. Proficient in Verilog language, proficient in vivado environment.

3. Experience in high-speed transmission interface serdes development or ASIC front-end design experience is preferred.

4. Have a good team spirit, positive work attitude and strong sense of responsibility.