Zhi Xing
Zhi Xing

High Performance Chiplet Die-to-Die Interconnect Total Solution

CLCI is a M2Semi’s solution for Die-to-Die interconnect IP.

 “Zhi Xing” is the latest D2D interconnect architecture of 2nd CLCI. It also includes MAC+PHY layer and the reference design of interconnect-package.

 It provides the built-in self-test (BIST) and external PHY-to-PHY link tests for on-chip testability and visibility into channel performance.

 It supports a variety of interface protocols and a variety of mainstream process nodes.

 It’s ready for MP. The silicon-proven EVB board can be provided to customer for evaluation.


Cloud Computing

Artificial Intelligence


Autonomous Driving

  Key Features:

Key Features

Its key feature can be summarized into three points: high performance, high reliability, and easy to use.


High Performance

- Already support 6/7/12/16nm

- Data rate up to 32Gbps per laneZhi Xing-更新

- Support 4/8/16/32 configurable data lanes

- Typical efficiency less than 1.0pJ/b

- Ultra low D2D latency, especially for xPU application

- Support max D2D connection distance 30mm


High Reliability

    - Silicon Proven, can provide evaluation kit and silicon report

     - BER<10-15 without ECC

     - Built-in self-test (BIST) & data retransmission mechanism

- Pass 1000h aging tests

- Pass various environment & reliability tests

- Already mass production in several projects


Easy to use

- Support AXI/ACE/CHI/CXS.B multiple system bus

- Support 2D/2.5D multiple packaging stack-up

- Proven silicon, evaluation platform, integration tools

- Support customized D2D connect feature

- Support D2D/C2C dual mode

- Support direct connection to the FPGA